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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8472 views
    0 replies
    Started over 4 years ago
    by Annie
  • Suggested Answer

    How to Modify RME Register Values and the LEGACYTZEN Signal on ARM V3AE CPU 0

    • Security
    • Development Boards
    39 views
    1 reply
    Latest 5 hours ago
    by Peter Harris Arm Employee Badge
  • Answered

    Enabling Arm CCA on Nvidia Jetson AGX Thor with Neoverse-V3AE CPU +1

    219 views
    1 reply
    Latest 2 days ago
    by Peter Harris Arm Employee Badge
  • Suggested Answer

    timing diagram 0

    • AMBA 5 CHI
    74 views
    1 reply
    Latest 4 days ago
    by Ben Hicks Arm Employee Badge
  • Answered

    Race Conditions in CXS interface protocol. Why? +1

    • CXS
    • Interface Bus Architecture
    66 views
    1 reply
    Latest 5 days ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Race Conditions in CXS interface protocol. Why? 0

    • CXS
    • Interface Bus Architecture
    72 views
    0 replies
    Started 5 days ago
    by SY FPGA
  • Suggested Answer

    CPAKs: Cycle accurate simulator/emulator for a Cortex M4 processor based board 0

    • Cycle Performance Analysis Kits
    • Cortex-M4
    100 views
    2 replies
    Latest 5 days ago
    by Mustapha Ghliss
  • Not Answered

    DMA Controller PL230 - Representation of PL230_DMA_CHNL_BITS 0

    • Architecture
    • DMA Devices
    • PrimeCell µDMAController (PL230)
    76 views
    0 replies
    Started 8 days ago
    by hk_007
  • Not Answered

    Enabling CCA on NVIDIA Jetson AGX Thor with Neoverse-V3AE CPU​ 0

    • Neoverse V3
    • Security
    83 views
    0 replies
    Started 10 days ago
    by Junjie Huang
  • Not Answered

    Cortex-R52+ External abort pending 0

    • Cortex-R52+
    86 views
    0 replies
    Started 12 days ago
    by Changjiang
  • Not Answered

    Setting up cache coherent transactions using CCI-500 0

    • Cortex-A72
    • Cache coherency
    • ACE
    • ACE-Lite
    • CoreLink CCI-500 Cache Coherent Interconnect
    97 views
    0 replies
    Started 14 days ago
    by Salkin
  • Not Answered

    ARM v8 SMMU Stage 2 translation fails 0

    • SMMUv3
    • Armv8-A
    402 views
    7 replies
    Latest 14 days ago
    by Dileep D R
  • Not Answered

    How to Define msi_msg for Software-Generated Interrupts with GICv3 ITS? (linux kernel 6.12.y) 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    135 views
    1 reply
    Latest 15 days ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    what is difference between read unique and clean unique? 0

    79 views
    0 replies
    Started 16 days ago
    by Tom T
  • Suggested Answer

    Clock Gating Cell Missing Module 0

    • Clocking Structures & Timing Mechanisms
    267 views
    3 replies
    Latest 20 days ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    CMSDK Compile Error for Cortex-M0 0

    64 views
    0 replies
    Started 20 days ago
    by Alarik Unggul Yudhatama Sukadis
  • Suggested Answer

    order problem 0

    • AXI4
    356 views
    5 replies
    Latest 21 days ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    axi ID problem 0

    85 views
    0 replies
    Started 21 days ago
    by Tom T
  • Suggested Answer

    Interrupt table and handling in cortex-m0+ assembly 0

    • Cortex-M0+
    • Arm Assembly Language (ASM)
    162 views
    1 reply
    Latest 27 days ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    AArch64 - VMSAv8 - TLB - Where to store the ASID in block/page table entry 0

    • AArch64
    • Memory Management Unit (MMU)
    280 views
    1 reply
    Latest 29 days ago
    by Martin Weidmann Arm Employee Badge
>
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