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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3630 Questions
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  • Answered

    Software level TrustZone for Cortex-M3/M4/M7 devices 0

    • AMBA 3 TrustZone Interrupt Controller (SP890)
    • Arm Trusted Firmware
    • Arm Architecture tools
    • TrustZone Controllers
    • Trusted Firmware-M
    • Armv7-M
    • TrustZone Address Space Controllers
    • GNU Arm
    • Trusted Execution Environment (TEE)
    • TrustZone
    3433 views
    4 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    how does processor identify itself 0

    1154 views
    1 reply
    Latest over 2 years ago
    by EllieC Arm Employee Badge
  • Not Answered

    Cortex R5 - TCM memory MPU setting 0

    1617 views
    1 reply
    Latest over 2 years ago
    by shalmana
  • Not Answered

    Cortex-A53 MMU: Contiguous bit at EL3 0

    • Cortex-A53
    • AArch64
    • Memory Management Unit (MMU)
    984 views
    0 replies
    Started over 2 years ago
    by bradbqc
  • Not Answered

    AHB2 split and RETRY operations in Single Transfer type and last beat of Burst transfer type 0

    1414 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    TrustZone in ARM Cortex M3 0

    • Trusted Firmware-M
    • Cortex-M3
    • Trusted Execution Environment (TEE)
    2303 views
    5 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    how to do cache line scan test? 0

    • Cortex-A53
    • Cache Management
    • Cortex-A
    806 views
    0 replies
    Started over 2 years ago
    by WatterCutter
  • Not Answered

    "bus error" when using arm neon intrinsics "vld2q_f32 " on MT676x 0

    760 views
    0 replies
    Started over 2 years ago
    by jeffery-work
  • Not Answered

    pilatus pipeline depth 0

    1027 views
    0 replies
    Started over 2 years ago
    by minmin
  • Suggested Answer

    Crash on "push rbp" 0

    2898 views
    6 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    cache contents miss fit with main tlb 0

    2159 views
    5 replies
    Latest over 2 years ago
    by WatterCutter
  • Not Answered

    [ARMV8] dmb nshld vs dmb ishld -- practical differences? 0

    • Armv8-A
    4538 views
    8 replies
    Latest over 2 years ago
    by a.surati
  • Not Answered

    Question about DSU behavior which is connected to an interconnect through CHI Interface 0

    • AMBA 5 CHI
    • DSU
    1477 views
    1 reply
    Latest over 2 years ago
    by user_1709
  • Not Answered

    Is it transparent to software that Cortex-A510 2 cores share VPU in a complex? 0

    • Cortex-A
    1276 views
    1 reply
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    VM Passthrough LPIs in GICv3 and priority drop 0

    1970 views
    2 replies
    Latest over 2 years ago
    by IMPL_DEF
  • Answered

    ARMv7: Default Memory map in case Write-Through is not supported 0

    • Cache Management
    • Memory Protection Unit (MPU)
    1853 views
    2 replies
    Latest over 2 years ago
    by Peter Happ
  • Not Answered

    PL390 GIC priority setting 0

    • Cortex-A Platforms Software
    • Baremetal
    1582 views
    2 replies
    Latest over 2 years ago
    by Alex_Chun
  • Not Answered

    Does apple M1 pro cpu support arm SVE? 0

    1862 views
    0 replies
    Started over 2 years ago
    by flyinghometown
  • Suggested Answer

    Cortex M4- leaving handler mode. 0

    • Interrupt Handling
    2009 views
    3 replies
    Latest over 2 years ago
    by dreamland7707
  • Not Answered

    Cortex-a8 - Disable L2 Cache 0

    • U-Boot
    • BeagleBone Black
    • Cortex-A8
    2271 views
    4 replies
    Latest over 2 years ago
    by Lucas Cunha
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