Dear All,
I am trying to understand the AHB2, For the single transfer type and the Last beat of burst transfer type if RETRY/SPLIT response is received, then IDEAL cycle is sent by Previous master(M1) or present master(M2)?
and please comment on HGRANT, HMASTER signals in 3rd and 4th cycleFYI:I took a 25% clock cycle delay to reflect the transition for each signal
Thanks in advance
Before trying to answer your question, can I ask if you are really using AHB in a design, or is this just academic interest ?
The reason I ask is that the original AHB protocol was replaced about 20 years ago by AHB-lite. One problem with AHB was that performance in a multi-master system wasn't great as only one master could be active at a time on the shared bus.
So AHB-lite came about because systems tended to implement just one master on a bus, and then use a BusMatrix interconnect to route transfers from each master layer to all the shared target slaves in the system. As we then only had one master per layer, we didn't need any bus arbitration signals, and we didn't need the SPLIT or RETRY responses. So AHB-lite is based on the original AHB, but with all the multi-master support removed.
AHB-lite, or the newer AHB5 protocols would be much better protocols to use or study in my opinion.
But to answer your AHB questions, bus arbitration handed over control of the bus in separate address and data phases, so in your diagram when the new master M2 is signaling the new address phase transfer, the data phase signals are still being routed to and from M1, so the RETRY/SPLIT is only relevant to M1. M2 will just see the 2-cycle RETRY/SPLIT response as a wait state, so will just hold HTRANSM2 at NONSEQ. M1's HTRANSM1 output could change to IDLE in response to the RETRY/SPLIT, but the system won't see this as the arbiter controlled address phase MUX will not be looking at M1 outputs.
Note that as HREADY is low in the first cycle of the 2-cycle RETRY/SPLIT response, this means M2 will keep its new address phase outputs constant, so HTRANSM2 will remain at NONSEQ, HADDRM2 won't change, and so HSEL2 will remain high.
Similarly HWDATA will be Data(A) in both the cycles you have labelled as the final data phase takes 2 cycles, and the bus master handover of the data phase signals doesn't happen until this data phase completes.
I don't see any problems with your HGRANT and HMASTER signals in cycles 3 and 4, or in any of your cycles; they look fine to me. I might question whether the timing of HBUSREQ_M2 is correct (you have labelled both requests as M1), but the timing of the second request seems to go low just as HGRANT goes high. This could just be a coincidence, but M2 can't see HGRANTM2 go high until the next HCLK rising edge, so there would normally be a one cycle delay from being granted to when the request would be removed.
Hopefully that helps you understand some of what is happening when bus master handover occurs, but I would think that it would be better using or studying the newer AHB-lite or AHB5 protocols, both of which are widely used.