cache contents miss fit with main tlb

my question is:

1、does this mean no data from 0x30000000  was cached ?

2、what's the reason cause this?

WatterCutter said:

2、enable MMU

3、setup page table

4、change memory attr of address space 0x30000000-0x3020000000 (sram) as  inner shareable|write back|r/w allocate

This might just be how you described the steps, but you really need to have done (3) before (2).

In step (4), did you invalidate the TLB after changing the translation table entry?  (The Arm Arm has an example sequences in K13.5.3 - TLB maintenance instructions and barriers).

What did the translation table entries for 0x30000000 say before you modified them in step (4)?

If you create the translations table with 0x30000000 already marked as IS/WB/RW before enabling the MMU, do you then see 0x30000000 in the cache after (5)? 

My suspicion is that you're not invalidating the TLBs in step (4), and thus the MMU is using a stale translation

In step (2), the initial translation table should at least mark where you're executing from as Normal.  Strictly speaking, it is not legal to execute instructions from regions marked as Device, and we usually recommend that all Device regions are also marked as not executable (XN=1) to avoid potential speculative instruction fetches from Device regions.  See here https://developer.arm.com/documentation/102376/0200/Device-memory 

In step (4), you wrote "NORMAL/IS/WT/RW".  Many Arm cores don't support Write-Through (WT) and will treat WT regions as effectively Non-cacheable.  You'll need to check the TRM for the processor your using to know whether that's true for yours.  But try using write-back (WB) instead,

Another potential gotcha is setting different inner vs outer cache-ability settings.