Cortex-a8 - Disable L2 Cache

Hey Guys,

First of all, I'm a total beginner on arm programming so I'm sorry if what I'm asking is too obvious or something like that.

So, I want to make some analysis with my L2 cache disabled. I'm running an U-boot environment, bare-metal, on my BeagleBone black and I'm trying to disable the cache following the steps provided on:

https://developer.arm.com/documentation/ddi0344/k/level-2-memory-system/enabling-and-disabling-the-l2-cache-controller

My code is something like this:

asm volatile("MRC p15, 0, %0, c1, c0, 0\t\n": "=r"(controlRegister)); //Retrieve Control Register
controlRegister = controlRegister & ~(1u << 2); //change Bit C to 0;
asm volatile ("MCR p15, 0, %0, c1, c0, 0\t\n" :: "r"(controlRegister)); //write new value

I know this is only the first step(disable C bit), but I'm having trouble accomplishing it. The problem is, when i try to write the new value and then check if it was write correctly, the value retrieved is 00000000.

Am I doing something wrong? Is there some kind of access level that I need to have to accomplish it? If so, how can I do it?

Regards,

Lucas Cunha