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Hello,
I am currently having a strange behavior when disabling the MPU and now I am wondering about one point there.
In the default memory map of the ARMv7 there are memory regions that use "Write-Through Cacheable" in case cache is enabled and default memory is used.
Now the Cortex-R7 that, does not support Write-Through:
My question is: What is the caching strategy for the Cortex-R7 for the memory regions that would in the default memory map be "Write-Through Cacheable".
Thanks and regards,
Peter
The Cortex-R7 will treat regions marked as write-through as effectively Normal non-cacheable.
One way to think of cache-ability attributes is saying what the processor is permitted to do. It's permitted to cache this region as cache-able with WT, but it's free to do something more conservative such as not caching it.
Thanks, that explains the behavior I see.