cache contents miss fit with main tlb

since I did:

1、set I and C bit in SCTLR_EL3

2、enable MMU

3、setup page table

4、change memory attr of address space 0x30000000-0x3020000000 (sram) as  inner shareable|write back|r/w allocate

5、read and write 0x30000000 more than 2 times 

I found that：

1、L1 cache contes only contains addresses related with page table （0xFXXXXXXX-)

2、main TLB contains addresses related with both page table and 0x30000000

my question is:

1、does this mean no data from 0x30000000  was caches ?

2、what's the reason cause this?

thanks.