Cortex-A53 MMU: Contiguous bit at EL3

Is the `contiguous` bit in a (VMSAv8-64) block/page descriptor utilized for EL3 translations?

I can see here that there is a `contiguous` field in the IPA cache RAM, but I don't see any mention of it in the Main TLB RAM. Given that EL3 translations are only a single stage, my understanding is that the IPA cache RAM isn't relevant but I'm wondering if there's any internal logic to combine contiguous regions into a single entry in the main TLB. I also see that the main TLB splits 1 GB blocks into two 512 MB entries so this question is only about the smaller block sizes and page entries.