Cortex R5 - TCM memory MPU setting


I am seeing conflicting information regarding TCM MPU setting,

"TCMs always behave as Non-cacheable Non-shared Normal memory, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM"

"Any address in an MPU region with device or strongly-ordered memory type attributes is implicitly given execute-never (XN) permissions. If such an address is also in a TCM region, XN permissions are applied to TCM accesses to that address. None of the other device or strongly-ordered behaviors apply to an address in a TCM region."

so does this mean if TCM memory is configured with Execute permission and Strongly-ordered, Would it still become Execute Never permission?