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Is it transparent to software that Cortex-A510 2 cores share VPU in a complex?

Hello,

Cortex-A510 TRM descibes that within a dual-core complex, VPU is shared between cores.

If the two cores in one complex use VPU simultaneously, how to handle the access conflict?

Does the software need resolve exclusive access on VPU? Is it transparent to software?

Best Regards,

Yan

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