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TrustZone for Armv8-M forum
  • Description Your first stop for all information regarding Arm TrustZone for Armv8-M, which brings security to the smallest of Arm Cortex processors by means of hardware-enforced isolation. Keep up with leading-edge information and get your questions answered.
  • Threads 88 Questions
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Unanswered questions
  • Lordeon
    Switching from 32bit to 64bit
    Suggested Answer 6 months ago
  • Michael Jung
    Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception
    Answered 2 months ago
  • val
    The Monitor
    Answered over 5 years ago
  • kappajacko
    Are the IDAU NS and NSC signals assumed to be mutually exclusive?
    Not Answered 2 months ago
  • Daniel Oliveira
    Arm Musca A1 - SRAM0 MPC Security attribute during boot
    Suggested Answer 6 months ago
Related tags
  • ACE
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  • Cortex-M
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  • Cortex-M33
  • Interrupt
  • Linux
  • Memory
  • Security
  • TrustZone
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TrustZone for Armv8-M forum

  • Suggested Answer

    Switching from 32bit to 64bit 0

    2976 views
    2 replies
    Latest 1 month ago
    by Zenon Xiu (修志龙)
  • Answered

    Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception 0

    • Real Time Operating Systems (RTOS)
    • Trusted Firmware-M
    • TrustZone for Armv8-M
    • Armv8-M
    1138 views
    3 replies
    Latest 1 month ago
    by Michael Jung
  • Answered

    The Monitor 0

    • TrustZone
    5872 views
    4 replies
    Latest 2 months ago
    by yufeifei
  • Not Answered

    Are the IDAU NS and NSC signals assumed to be mutually exclusive? 0

    628 views
    0 replies
    Started 2 months ago
    by kappajacko
  • Discussion

    SAU vs. IDAU in a System with Multiple Masters

    • Security
    • TrustZone
    • Armv8-M
    11383 views
    5 replies
    Latest 2 months ago
    by Chris Reed
  • Suggested Answer

    Arm Musca A1 - SRAM0 MPC Security attribute during boot 0

    • Musca-A
    • TrustZone for Armv8-M
    • CoreLink SSE-200
    3055 views
    2 replies
    Latest 2 months ago
    by Daniel Oliveira
  • Not Answered

    MPU_S and cmse_check_address_range 0

    3611 views
    0 replies
    Started 10 months ago
    by EugeneH
  • Answered

    Non-secure configuration of UART1 on Arm Musca-A1 0

    • Musca-A
    • TrustZone for Armv8-M
    8915 views
    4 replies
    Latest over 1 year ago
    by Daniel Oliveira
  • Not Answered

    Limit NSC calls to specified RTOS tasks. 0

    6887 views
    1 reply
    Latest over 1 year ago
    by Ken.Liu
  • Not Answered

    How to write values ​​from secure code to non-secure memory. 0

    • TrustZone for Armv8-M
    7072 views
    1 reply
    Latest over 1 year ago
    by Uma Ramalingam
  • Not Answered

    PendSV target secure state 0

    5979 views
    1 reply
    Latest over 1 year ago
    by Uma Ramalingam
  • Not Answered

    What is the best location of RTOS ? 0

    6094 views
    0 replies
    Started over 1 year ago
    by EugeneH
  • Discussion

    What is the top level difference in features between Cortex-M33 and Cortex-M4?

    • Cortex-M23
    • Trace
    • ACE
    • AXI
    • CHI
    • Security
    • Cortex-M3
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Cortex-M4
    • Internet of Things (IoT)
    • AHB
    • Interrupt
    24379 views
    1 reply
    Latest over 1 year ago
    by bodybeacon
  • Not Answered

    Use DS-5 MPS2_CM33 FVP in non-secure mode ? 0

    6627 views
    0 replies
    Started over 1 year ago
    by ilchang
  • Not Answered

    Calling non-secure Reset Handler from Secure main 0

    • Cortex-M33
    • Armv8-M
    6032 views
    1 reply
    Latest over 1 year ago
    by Radhika Raghavendran
  • Not Answered

    SAU configuration failure 0

    • TrustZone for Armv8-M
    • Cortex-M33
    6109 views
    1 reply
    Latest over 1 year ago
    by Radhika Raghavendran
  • Not Answered

    Context protection when calling a secure function(NSC) in a non-secure interrupt function 0

    14348 views
    10 replies
    Latest over 1 year ago
    by Yang Zhang
  • Not Answered

    How to place FreeRTOS in secure memory and the user tasks in non-secure memory? 0

    • TrustZone
    • Armv8-M
    31172 views
    21 replies
    Latest over 1 year ago
    by Joseph Yiu
  • Answered

    Boot sequence and secure boot 0

    • Cortex-M23
    • Cortex-M
    • Armv8-M
    9487 views
    2 replies
    Latest over 1 year ago
    by LukaP
  • Not Answered

    Non-secure code calling secure code - Boot Loaders 0

    7129 views
    2 replies
    Latest over 1 year ago
    by vinkot
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