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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3583 Questions
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  • Answered

    BP147(TZPC) and TZC-380 0

    5739 views
    4 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    Usage of gathering and reordering in the ARMv8 0

    • Armv8
    4989 views
    1 reply
    Latest over 11 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Does AMBA 4 ACE backward compatible with AXI3? 0

    • AMBA 4
    • AXI3
    • ACE
    8490 views
    4 replies
    Latest over 11 years ago
    by Neil Parris Arm Employee Badge
  • Answered

    Question regarding A15 L2ACTLR register programming (auto clock gating) 0

    • Cortex-A15
    4908 views
    3 replies
    Latest over 11 years ago
    by chinatiger
  • Answered

    Motherboard provider with Cortex-A53 or ARM Cortex-A57 +1

    • Cortex-A53
    • Cortex-A57
    • Armv8
    6306 views
    1 reply
    Latest over 11 years ago
    by Alban Rampon
  • Answered

    Cortex-A9 secondary boot Procedure 0

    • Cortex-A9
    • Cortex-A
    • Linux
    9008 views
    2 replies
    Latest over 11 years ago
    by niyas
  • Answered

    Enable Reentrant interrupt handlers in kinetis K70 0

    • Interrupt
    10179 views
    6 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Instruction availability 0

    4158 views
    2 replies
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    Generic Timer - Is it optional? 0

    • Armv8
    • Armv8-A
    6377 views
    3 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    Multi copy atomicity and usage of observers 0

    8901 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Cortex-M3:Little endian 0

    • Cortex-M3
    • Cortex-M
    10716 views
    1 reply
    Latest over 11 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    What is single-copy atomicity and how it is used in the software programming? 0

    11692 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    LDM to LTP Reason 0

    9248 views
    5 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    What is the PMU counter resolution when the processor switches between 64-bit and 32-bit mode? 0

    • AArch64
    • Armv8
    • 64-bit
    • AArch32
    5499 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Difference between co-processor registers and System registers 0

    • Armv7
    • Armv8
    4295 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Code execution taking ages!! +1

    • Cortex-M
    3605 views
    1 reply
    Latest over 11 years ago
    by Kashif
  • Answered

    Using shareable attribute in MPU configuration of Cortex R4 +1

    • L1
    • AXI
    • Cache
    • Memory Protection Unit (MPU)
    • L2
    • Cortex-R4
    6552 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    What's the Cortex-A12 Main Bus Interface? 0

    • Cortex-A12
    • Cache coherency
    • ACE
    9424 views
    7 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    question about TrustZone's third party IP 0

    3306 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Organization of startup from internal flash of Cortex M3 0

    • Cortex-M3
    5272 views
    2 replies
    Latest over 11 years ago
    by Volker Kugler
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone