Hi,
In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically Tagged). I know the advantages and disadvantages of using either VIPT/PIPT, but why not make both caches VIPT, or both PIPT?
Also, I'm trying to understand how VIPT can even work for certain A8 configuration in an OS like Linux, that uses 4KB pages?
For example, the ARM VMSA says, L1 caches have..
- fixed line length of 64 bytes
- support for 16KB or 32KB caches (Let's Pick 32KB.)
- an instruction cache that is virtually indexed, IVIPT
- 4-way set associative cache
So from this, the no.of cache lines would be = 512
Size of a cache line = 64 bytes (lower 6 bit's of address would be an offset within cache line)
As there are 4 ways, so the no.of indexes would be = size of cache / no.of ways = 512 / 4 = 128 (index will be 7-bit)
The rest of the bits would go for the physical tag, (32 - 6 - 7 = 19).
For VIPT to work (That is the translation of the VA -> PA should happen in parallel to the Cache Index lookup), the bits comprising of the Index and the the Cache Line offset, should not change between the VA and PA).
Now, if we take an OS like Linux which uses pages of size 4KB, only the lower 12-bits are constant between the VA and the PA, but the above VIPT configuration described requires the lower 13 bits (7 bits for Index and 6 bits for Cache line offset) to be fixed. So in this case, how would VIPT work for the instruction cache?
thanks,
-Joel