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question about Part C: Debug Architecure in ARMv7 ARM.pdf

hi, experts:

i am studying ARMv7 ARM.pdf's Part C: Debug Architecure.

In Chapter C8.1.3, it described :

Software can access DBGDSCRext,  DBGDTRRXext, and DBGDTRTXext through:

.the CP14 interface:

  — in v7 Debug it is IMPLEMENTATION   DEFINED if these registers are vi sible in the CP14 interface

  — in v7.1 Debug these registers are required in the CP14 interface

.the memory-mapped interface, if implemented

.the external debug interface

...

...

So, i have 2 questions:

1. access DBGDSCRext,  DBGDTRRXext, and DBGDTRTXext through external debug interface.

    through CP14/mem-mapped, it's easy to understand.

    so how to access these regs through external debug interface?

    Through JTAG/SWJ?

2. Chapter C11 : the debug register

    So, take a Cortexx-A7 as an example:

     how to get V7 debug memory-mapped region's base addr?

     This chapter only described the registers' offset in mem-mapped region, not describe how to obtain this base addr.

best wishes,

Parents
  • so how to access these regs through external debug interface?

    You can access debug registers though either JTAG or SWJ using a DAP (Debug Access Port) module

    how to get V7 debug memory-mapped region's base addr?

    Processor will provide the DBGROMADDR signal to let you specify the Debug APB memory map.

    For example, in A7 processor:

    The DBGROMADDR and DBGSELFADDR signals enable the processor to determine parts of the Debug APB memory map.

    When DBGROMADDRV is HIGH, DBGROMADDR[39:12] indicate the most significant bits of the address of the DAP ROM table in the system memory map for software accesses into the debug APB bus through the DAP APB multiplexer.

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  • so how to access these regs through external debug interface?

    You can access debug registers though either JTAG or SWJ using a DAP (Debug Access Port) module

    how to get V7 debug memory-mapped region's base addr?

    Processor will provide the DBGROMADDR signal to let you specify the Debug APB memory map.

    For example, in A7 processor:

    The DBGROMADDR and DBGSELFADDR signals enable the processor to determine parts of the Debug APB memory map.

    When DBGROMADDRV is HIGH, DBGROMADDR[39:12] indicate the most significant bits of the address of the DAP ROM table in the system memory map for software accesses into the debug APB bus through the DAP APB multiplexer.

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