Hello,
in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate the component allows me to only set address widths which are a power of 2. I'm wondering if this is simply a restriction of the BFM or if this restriction is originating from the specification?
Best regards
Martin