We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello Everyone,
[This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?
In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) then the data can be sent as following
1) A1 B1 A2 B2 (interleaved)
2) A1 A2 B1 B2 (In-order)
3) B1 B2 A1 A2 (out of order)
....
Please let me know if my understanding is not correct
[AXI4] Do we support write out-of order write in AXI4? (I know that we removed WID signal from write data channel)
In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave?(without having interleaving/out-of-order support)
Thanks Xingguang.
Hello,
>[This not specific to AXI3/4] Can someone give an example on how write data interleaving works?
Note that write data interleaving is only applicable to AXI3. There is no write data interleaving in AXI4.
Examples: see 1) 2) 3) below.
>Is it used only when we have multi-master cases?
No.
>or its possible with single-master cases also?
Yes.
>In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) then this can be interleaved as following
Let's assume that A is issued first. With that said:
>1) A1 B1 A2 B2 (interleaved)
This is legal.
>2) A1 A2 B1 B2 (In-order)
>3) B1 B2 A1 A2 (out of order)
This is illegal. AXI3 requires that the first WDATA item must be issued in the same order as the write address, regardless of the write ID. Since A is issued first in this example, A1 must occur first.
>....
Another legal example would be: A1 B1 B2 A2
>Please let me know if my understanding is not correct
>
>[AXI4] Do we support write out-of order write in AXI4? (I know that we removed WID signal from write data channel)
No. AXI4 has removed the support for write data interleaving. WID is removed in AXI4, so WDATA must strictly follow the AW order.
>In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave?
First of all, an AXI4 master must not issue interleaved write data.
Secondly, the interconnect must ensure that write data is not interleaved when merging data streams from different masters to the same slave.
Regards,
Xingguang