Hello Everyone,
[This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?
In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) then the data can be sent as following
1) A1 B1 A2 B2 (interleaved)
2) A1 A2 B1 B2 (In-order)
3) B1 B2 A1 A2 (out of order)
....
Please let me know if my understanding is not correct
[AXI4] Do we support write out-of order write in AXI4? (I know that we removed WID signal from write data channel)
In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave?(without having interleaving/out-of-order support)