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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3624 Questions
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  • Not Answered

    ARM Cortex-M3 Priority 0

    604 views
    0 replies
    Started 10 months ago
    by vignesh varadaraj
  • Not Answered

    A53 core not going into WFI sometimes. 0

    1032 views
    2 replies
    Latest 10 months ago
    by Diptendu
  • Suggested Answer

    Clarification on Instruction Cache Availability in Cortex-M33 IP 0

    1454 views
    1 reply
    Latest 10 months ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    How to know the APSEL number when there are multiple APs? 0

    • adi
    459 views
    0 replies
    Started 10 months ago
    by si huibin
  • Not Answered

    TF-M PSA Crypto Random 0

    • PSA
    • TF-M
    1578 views
    4 replies
    Latest 11 months ago
    by Fran DP
  • Not Answered

    Unable to read currentel 0

    • a72
    • Armv8-A
    1379 views
    3 replies
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    SOC sensor chips 0

    414 views
    0 replies
    Started 11 months ago
    by Brahm
  • Suggested Answer

    Difference between System mode, User mode and Supervisor mode in Cortex R. 0

    • Cortex R
    1781 views
    1 reply
    Latest 11 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

    939 views
    1 reply
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

    • GICv3/v4
    • Armv8-R
    1123 views
    2 replies
    Latest 11 months ago
    by ShihHsun Chang
  • Not Answered

    Question about ITS Retry Behavior after Stalled MAPD Command 0

    1048 views
    2 replies
    Latest 11 months ago
    by steve jeong
  • Suggested Answer

    AXI4 ordering Model. 0

    • AXI4
    1204 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
    1180 views
    1 reply
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
    2296 views
    6 replies
    Latest 11 months ago
    by ele
  • Not Answered

    Is there any way to use 2-DSU IPs in a same NI-Bus ? 0

    • DSU-120
    • DSU
    411 views
    0 replies
    Started 11 months ago
    by Sangu Park
  • Answered

    Secure Mode Switching in R5 0

    • cortexr5
    992 views
    1 reply
    Latest 11 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
    • Cortex-A
    413 views
    0 replies
    Started 11 months ago
    by yiduan su
  • Answered

    What will happen when cacheline is mismatch 0

    • Cache
    • Cache Management
    • Cortex-A
    • Cortex-M
    1270 views
    2 replies
    Latest 11 months ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    1031 views
    1 reply
    Latest 11 months ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    588 views
    0 replies
    Started 11 months ago
    by Adithya SM
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