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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3624 Questions
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  • Answered

    GIC Interrupt handling in Linux 0

    4334 views
    2 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Master slave connection for BP210 0

    1206 views
    2 replies
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    compliance test for arm M4 for post silicon +1

    789 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    GIC Interrupt handling 0

    4001 views
    4 replies
    Latest over 2 years ago
    by ChanelRogahn
  • Not Answered

    Cortex-M4F: Crash when using FPU and math with literal 0

    • Cortex-M4
    1426 views
    1 reply
    Latest over 2 years ago
    by Hans Schneebauer Arm Employee Badge
  • Answered

    Read memory block loaded by bootloader at EL3, but on EL2 0

    • Cortex-A53
    • AArch64
    • virtualization
    • Armv8-A
    • Embedded Hypervisor
    • Memory Management Unit (MMU)
    3871 views
    8 replies
    Latest over 2 years ago
    by pcarmo
  • Suggested Answer

    broken link arm infocenter 0

    • Cortex-M0
    • FAQ
    1837 views
    2 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    why is down counter more efficient than up counter 0

    1848 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    About Exception Handler Return Address 0

    • Arm7
    • Armv7 Exception Model
    • Cortex-R5
    • 12 (Debug Monitor)
    • External Hardware Debug
    • Debugging
    • Debugger
    2269 views
    4 replies
    Latest over 2 years ago
    by shincm
  • Answered

    Cortex M7 abnormal instruction-fetch behavior 0

    4646 views
    3 replies
    Latest over 2 years ago
    by shaoxuan
  • Not Answered

    IN the cortex -m7, After ITCMERR is happened , the cpu will do what? 0

    585 views
    0 replies
    Started over 2 years ago
    by yangfang
  • Not Answered

    The debugger cannot reconnect without a hard reset of the Cortex-M55. 0

    • Cortex-M55
    • Armv8-M
    • Serial Wire Debug
    • Debug Access Port (DAP)
    922 views
    0 replies
    Started over 2 years ago
    by N_MIYA
  • Answered

    Pending Interrupt is not signaled to the PE 0

    • Interrupt Handling
    • AArch64
    • GICv3/v4
    • Fixed Virtual Platforms (FVPs)
    • Hypervisor
    3437 views
    2 replies
    Latest over 2 years ago
    by Martin.S
  • Not Answered

    The CPU how deal with next behavior when signal ITCMERR is set HIGH in the ITCM protocol.Or how to draw the next diagram sequence? 0

    677 views
    0 replies
    Started over 2 years ago
    by yangfang
  • Not Answered

    Arm-v7r Cortex-R5F How to Access CP14 Register 0

    • Arm7
    • Cortex-R5
    • External Hardware Debug
    • Learn the Architecture
    • Debugging
    824 views
    0 replies
    Started over 2 years ago
    by shincm
  • Not Answered

    Cortex M0+ SWD debug reference implementation 0

    • Debugger
    • Serial Wire Debug
    1185 views
    0 replies
    Started over 2 years ago
    by SamPfarrer
  • Not Answered

    Does using CMSIS-dsp library cost current? 0

    • Digital Signal Processor (DSP)
    • CMSIS
    705 views
    0 replies
    Started over 2 years ago
    by jason_chen
  • Suggested Answer

    get cycle counts after reset for a53 processor 0

    • Cortex-A53
    • Real-Time
    4146 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Is there anyway to build 3D CI-700 Mesh configuration using Socrates ? +1

    1156 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    IERRR bit set before GIC initalisation 0

    • GICv3/v4
    • CoreLink GIC-600
    • CoreLink GIC-600 Generic Interrupt Controller
    736 views
    0 replies
    Started over 2 years ago
    by Namu
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