It is a simple design query for generating BP210 bus matrix using ARM Socrates.
For generating bus matrix BP210(which only supports AHB-Lite components), how to specify master to slave connection when a slave can have multiple shared address map across different masters.
Let say s1 has the shared address mapping for both m3 and m4. How do we generate BP210 bus model with such an addressing scheme.
If I configure S1 with 2 address region, one for m3 and another m4 and try to generate bus matrix, I get error-
Error: Interface SI1 address region 'MI3: A0000000-AFFFFFFF' overlaps with another address region 'MI0: A0000000-AFFFFFFF'!Error: Interface SI1 address region 'MI4: A0000000-AFFFFFFF' overlaps with another address region 'MI0: A0000000-AFFFFFFF'!
Socrates GUI has no option for specifying multiple master for a single slave.
Please let me know how to configure such scenarios, I have many 7-8 slaves/ 5-6 masters which follow such overlapping address mapping scheme.
Please raise an official support request via the menu above.
Just in case I can quickly answer your question and save you having to raise an official support request as Ronan suggested, does the following help ?
The terminology used in the BusMatrix to refer to the interfaces can be a bit confusing. The SI references are for the "input ports" on the BusMatrix that the upstream AHB-lite logic will be driving transfer requests into (they appear on the BusMatrix as an AHB-lite "subordinate" port). And the MI references are for the "output ports" that then drive the downstream targets for transfers (they appear as AHB-lite "manager" ports).
Whereas I think your table is describing the BusMatrix interfaces based on the component that connects to them.
So your external "Master" drives a BusMatrix "SI" port, and your external "Slave" is driven by a BusMatrix "MI" port.
When you then configure the BusMatrix address maps, you can specify a different address map for each SI to tell it how all the MI "targets" can be addressed.
Each SI address map needs to have unique address ranges allocated to each of the MIs it can connect to, so in your error message you have both MI0 and MI3 in the same A000_0000 to AFFF_FFFF address space for SI1. When SI1 receives a transfer request to A000_0000, it wouldn't then know which MI to route the transfer to.
Your "Slave1" can be accessed by both "Master3" and "Master4" at the same address range as long as you specify that address range in each of the address maps for "Master3" (SI3) and "Master4" (SI4).
The terminology confusion is that your "Master3" would be connected to "SI3" in the BusMatrix terminology, "Master4" is connected to "SI4",and finally "Slave1" would be connected to "MI1".
Hopefully that answers your question, but if not then please do as Ronan suggests so someone can look at your configuration in more detail.