Hey Experts
Got one basic question,
My IP generates edge trigger interrupt only , Can I program GIC to have level trigger IT
and vice versa
Thanks
Yes! :-)
You need to program the interrupt semantics (edge vs level) in the appropriate GICx_ICFRG<n>{E} register. On the assumption you're interrupt source is an SPI, the register will either be GICD_ICFGR<n>:
https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n---Interrupt-Configuration-Registers
Or, GICD_ICFGR<n>E:
https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n-E--Interrupt-Configuration-Registers--Extended-SPI-Range-
Note, if this is an MSI signalled via an ITS then in GIC terms it will be an LPI and LPIs are always edge.
More background info in the Learn the Architecture guide: Learn the architecture - Arm Generic Interrupt Controller v3 and v4
Thanks Martin,
This is quite clear from GIC perspective, about edge/level support
If I understand well, GIC can be programmed to level/edge as per IP specification.
But this can not convert the type of interrupt , correct ?
Example
1) If IP generates level trigger interrupt then GIC can be used as level or edge both
2) If IP generates, edge interrupt, then there is possibility GIC may loose some interrupt sampling, if programmed for level for this IP ?
Regards
Udit
uditknit said:But this can not convert the type of interrupt , correct ?
Correct. You need to configure the GIC to match how the device is driving the interrupt signal.
uditknit said:1) If IP generates level trigger interrupt then GIC can be used as level or edge both
No - that would likely cause you problems.
Let's take the Generic Timer as an example. The timer's interrupt uses level semantics and the interrupt is driven when:
Timer Condition Met: Comparator <= System Count
The timer interrupt is cleared by either disabling the timer or updating the comparator value to a bigger number.
Now imagine the timer goes off at time X:
Now this is the potentially problematic part - you'd assume that the new comparator value was enough into the future that the timer's interrupt condition was not met. But that's not guaranteed and there are reasons why it might not be true.
So let's assume that in this case the new comparator value means the timer IS STILL met and therefore the interrupt signal IS STILL asserted
And now we have a problem. The timer "thinks" it is sending an interrupt to the GIC, as it's asserting a level-sensitive signal. The GIC "thinks" there is no pending interrupt, as it "thinks" the signal is edge-triggered and it's only seen one edge.
Really the message is - software needs to program the GIC to match the sending devices. Having a miss-match will likely cause you interesting problems to debug
Thank you for answering, you made my day :)