I am working on a hypervisor running in EL2N (aarch64). I try to use the physical EL2 timer (CNTHP_*_EL2) to signal an interrupt to the hypervisor. I configured the counter and write to the timer value register. After the time has passed, the ISTATUS bit in CNTHP_CTL_EL2 is correctly set to 1, the IMASK bit is 0 all the time.
As detailed in "AArch64 Programmer's Guides Generic Timer" I configure INTID 26. It is set as a Group 1 NS interrupt, which I enable and set the priority to 0xa0. After the timer condition is met, the INTID shows up in ICC_HPPIR1_EL1 and reading GICR_ICPENDR0 also show that INTID 26 is pending.
Further checks I did to ensure the interrupt is enabled:
ICC_GRPEN1_EL1 is set to one, showing that group 1 interrupts are enabled for the current security state (non-secure)
ICC_GRPEN1_EL3 also shows that Group 1 NS interrupts are enabled
GICD_CTLR Affinity Routing is enabled and Group1NS Interrrupts are enabled
From my understanding the interrupt is configured correctly and should interrupt the execution on the PE (I only use 1 PE). However, this does not happen.
Can anyone help me in understanding why this is the case or which configuration I might have missed?
Any help is appreciated!
With kind regards
thank you for the detailed and helpful answer! ISR_EL1.I showed the interrupt is signalled and since PSTATE.I also did not mask exceptions I found the reason for my problem in HCR_EL2.IMO I thought it was only relevant for interrupts from lower ELs but apparently it is relevant for interrupts at any EL, good to know.
Know the interrupt handler is triggered as soon as the timer condition is met which is the expected result.
Thank you very much!