Hi.
We are now implementing and testing CM55 in our FPGA. For a very simple configuration, we use the startup code for the Generic Cortex-M55 device as is.
After the hard reset has been asserted, uVision allows you to load and debug (step-by-step) the program on the first connection.
However, if you exit debugging and try to load and debug the program again with a warm reset by sysresetreq, you will get a "Core cannot be stopped" error message that prevents the connection.
After reviewing the debugger logs, After writing 0xA05F0003 (indicating debug key and enable) to DHCSR(0xE000EDF0), I notice that the values read are different. First : 0x00130003 Second : 0x00110003
The second time the S_HALT bit is not set and appears to fail.
Do you have any clues to resolve this symptom?
Best regards.