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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3631 Questions
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  • Not Answered

    Can you tie off TLB if you're not using virtual memory? 0

    1177 views
    1 reply
    Latest over 2 years ago
    by 42Bastian Schick
  • Suggested Answer

    Is microSCU required for multi-cores to maintain coherency? +1

    1732 views
    3 replies
    Latest over 2 years ago
    by tjones95134
  • Answered

    Cortex-A15: How to access the Revision ID register, REVIDR 0

    • Cortex-A15
    1470 views
    2 replies
    Latest over 2 years ago
    by TimF
  • Suggested Answer

    Difference in coding format. 0

    • Base ISAs
    • SIMD ISAs
    1478 views
    2 replies
    Latest over 2 years ago
    by BobP
  • Answered

    SVC instruction execution inside the hard fault handler 0

    3380 views
    4 replies
    Latest over 2 years ago
    by Sudhu145
  • Not Answered

    How to automatically detect Cortex M7 ALU overflow ?? 0

    • Interrupt Handling
    • Cortex-M7
    • Arm Compiler for Embedded FuSa
    1351 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    What is the unit of PMHF for R52 IP FMEDA 0

    • Cortex-R52
    851 views
    0 replies
    Started over 2 years ago
    by pengfu xie
  • Answered

    Equivalent of SSE4.2 needed for ARM support to CNDP Project 0

    3124 views
    6 replies
    Latest over 2 years ago
    by Annie
  • Not Answered

    ARMV8 arch64 how to handle bus error and interrupt occur together 0

    2138 views
    2 replies
    Latest over 2 years ago
    by Thomas Coding
  • Not Answered

    Cortex-M7 Failing to read PPB ROM table 0

    1022 views
    0 replies
    Started over 2 years ago
    by Bert Hindle
  • Not Answered

    Debug Print Logs Display and Hardware Power Issue in KEIL uVision 5 (Cortex-M0) 0

    1420 views
    1 reply
    Latest over 2 years ago
    by Annie
  • Not Answered

    SMMUv2 IRQS per Context Bank 0

    • SMMUv2
    799 views
    0 replies
    Started over 2 years ago
    by Jorge
  • Not Answered

    The pipeline of add with lsl >4 in Neoverse N1 0

    • Documentation
    • Neoverse N1
    993 views
    0 replies
    Started over 2 years ago
    by Juneyoung Lee
  • Not Answered

    Can I use a Single Linux OS to schedule two DSU cluster? 0

    • Embedded Linux
    • DynamIQ
    2545 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Enabling MPU causes clearing of Stack in Cortex R5F 0

    • Cortex-R5
    1514 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Tail Chaining 0

    • Interrupt Handling
    1345 views
    1 reply
    Latest over 2 years ago
    by Sue Wu Arm Employee Badge
  • Suggested Answer

    Is PendSV or counterpart available on Cortex-A? 0

    • Cortex-A
    • 14 (PendSV)
    2143 views
    2 replies
    Latest over 2 years ago
    by AndyBlue
  • Suggested Answer

    Cortex-A78 NEON instructions timing 0

    2279 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    How to obtain the AArch64 memory management examples mentioned in the document "Learn the architecture - AArch64 memory management examples" 0

    • AArch64
    • Memory Management Unit (MMU)
    • Memory Management
    3535 views
    4 replies
    Latest over 2 years ago
    by zhanlang
  • Answered

    Cortex-M4F: Assembly instruction SMLAxy (and some others) gives wrong result 0

    • Cortex-M4
    2902 views
    2 replies
    Latest over 2 years ago
    by Evgen Volkov
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