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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    Can I use a Single Linux OS to schedule two DSU cluster? 0

    • Embedded Linux
    • DynamIQ
    2463 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Enabling MPU causes clearing of Stack in Cortex R5F 0

    • Cortex-R5
    1463 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Tail Chaining 0

    • Interrupt Handling
    1293 views
    1 reply
    Latest over 2 years ago
    by Sue Wu Arm Employee Badge
  • Suggested Answer

    Is PendSV or counterpart available on Cortex-A? 0

    • Cortex-A
    • 14 (PendSV)
    2111 views
    2 replies
    Latest over 2 years ago
    by AndyBlue
  • Suggested Answer

    Cortex-A78 NEON instructions timing 0

    2192 views
    1 reply
    Latest over 2 years ago
    by Zhifei Yang Arm Employee Badge
  • Answered

    How to obtain the AArch64 memory management examples mentioned in the document "Learn the architecture - AArch64 memory management examples" 0

    • AArch64
    • Memory Management Unit (MMU)
    • Memory Management
    3505 views
    4 replies
    Latest over 2 years ago
    by zhanlang
  • Answered

    Cortex-M4F: Assembly instruction SMLAxy (and some others) gives wrong result 0

    • Cortex-M4
    2868 views
    2 replies
    Latest over 2 years ago
    by Evgen Volkov
  • Suggested Answer

    What's the relationship between trace and SPE? 0

    • performance
    • arm streamline
    2195 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    ARMv8 trigger core dump 0

    1536 views
    2 replies
    Latest over 2 years ago
    by Pete_Gil
  • Not Answered

    A53: PMU - BUS_ACCESS_LD - Write-Streaming 0

    1421 views
    0 replies
    Started over 2 years ago
    by Chris_Ger
  • Not Answered

    CYCLONE V - HPS - DDR RAM CONTROL OVER JTAG WITH OPENOCD 0

    • Cortex-A9
    • JTAG
    • SoC FPGA
    • Baremetal
    1595 views
    0 replies
    Started over 2 years ago
    by ieeeHuseyin
  • Suggested Answer

    NIC400: What is the difference between ahblitetarget and ahbliteinitiator 0

    3526 views
    1 reply
    Latest over 2 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    ARMv8 Writing and reading to/from Debug Data Transfer Register 0

    3744 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [Cortex M0] tarmac on palladium emulator 0

    1096 views
    0 replies
    Started over 2 years ago
    by SujithCh8
  • Not Answered

    Cortex A9 L2 cache clean-invalidate timing issue 0

    • CoreLink L2C-310 Level 2 Cache Controller
    1115 views
    0 replies
    Started over 2 years ago
    by hilchenbach
  • Not Answered

    NVIC and/or USART appears to hold pending requests stuck (Cortex-M0 in STM32L071) 0

    995 views
    0 replies
    Started over 2 years ago
    by AGrigoriev
  • Not Answered

    What improvements does FEAT_DoPD provide? 0

    • Architecture
    • External Hardware Debug
    901 views
    0 replies
    Started over 2 years ago
    by srLeslie
  • Answered

    R5: Does the exception vector table reside in TCM if at 0x0000 0000 0

    • Armv7 Exception Model
    • Cortex-R5
    4126 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    What these system registers(such as S3_3_c15_c7_0) are used for in Cortex-A55? 0

    • Cortex-A55
    • Armv8-A
    3060 views
    2 replies
    Latest over 2 years ago
    by Emmy0
  • Not Answered

    Is the PLD instruction implemented on the Arm Cortex M4, and actually preloading the cache line? 0

    • performance
    • Instruction Sets
    • Armv7-M
    • Cache Management
    • Cache Architecture
    • Cortex-M4
    843 views
    0 replies
    Started over 2 years ago
    by Toarte Fretter
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