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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
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  • Answered

    Using interrupts not implemented as Software interrupts? 0

    • Cortex-M0
    • Cortex-M
    • Interrupt
    13272 views
    5 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Cortex-M3 pipelining of consecutive LDR instructions to different memory regions? +1

    • Cortex-M3
    • 15 (SysTick)
    • Memory
    17492 views
    14 replies
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Out-of-Order of Cortex-A15 core and an interrupt 0

    • Cortex-A15
    • Out-of-order Execution
    • Cortex-A
    6057 views
    4 replies
    Latest over 11 years ago
    by Michihiro Yamamoto
  • Answered

    how does ARMv8 switch to run application(EL0) from kernel(EL1)? 0

    • Armv8
    13048 views
    2 replies
    Latest over 11 years ago
    by yan.wy
  • Answered

    How to switch off 2nd core for Cortex-A9 0

    • Cortex-A9
    7943 views
    2 replies
    Latest over 11 years ago
    by Sherry
  • Answered

    What will I get if I operate p15 to switch to TZ mode when I'm right in TZ mode. 0

    • TrustZone
    • Processors
    8417 views
    7 replies
    Latest over 11 years ago
    by Jay Zhao
  • Answered

    LDM/STM interruption of Cortex-M7. 0

    • Cortex-M7
    • Interrupt
    5086 views
    1 reply
    Latest over 11 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    MCU Development - Endianness - Big Endian 0

    • Cortex-M7
    • Microcontroller (MCU)
    • Cortex-M
    • Internet of Things (IoT)
    10078 views
    4 replies
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    ARM Cortex-M3/M4 Toolchain and IDE 0

    • Tool
    • Toolchain
    • Cortex-M3
    • Cortex-M4
    7657 views
    2 replies
    Latest over 11 years ago
    by Guy Dillen
  • Not Answered

    Anyone for HORIZON 2020? 0

    • Internet of Things (IoT)
    4295 views
    3 replies
    Latest over 11 years ago
    by Mike Clark
  • Answered

    ARM communication with UART 0

    8021 views
    3 replies
    Latest over 11 years ago
    by wilber vargas
  • Answered

    The Non-Secure Access IDentity (NSAID) of TZC-400 0

    • AXI
    • CoreLink TZC-400
    9485 views
    2 replies
    Latest over 11 years ago
    by wangyong
  • Not Answered

    I would like to settle an argument with regards to Rockchip RK3288 Cortex-A17 specifications 0

    • big.LITTLE
    • Cortex-A12
    • Cortex-A17
    5729 views
    3 replies
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Use case of .cantunwind in ARM asm? 0

    • Arm Assembly Language (ASM)
    6896 views
    2 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    Cache and store buffer maintenance in cortex-a8! 0

    • Armv7
    • Cache coherency
    • Cortex-A
    • Cortex-A8
    8232 views
    6 replies
    Latest over 11 years ago
    by Hamed
  • Answered

    What will I get if I try to access SCR in cp15 when my core is in non secure mode. +1

    • TrustZone
    6236 views
    4 replies
    Latest over 11 years ago
    by Jay Zhao
  • Answered

    Which ARM core is best suited for DSP applications? 0

    • DSP
    • Cortex-R
    • Cortex-A
    8168 views
    5 replies
    Latest over 11 years ago
    by Dr. Paul Beckmann
  • Answered

    Code for integer division on Cortex-A8? 0

    • Cortex-A8
    16896 views
    12 replies
    Latest over 11 years ago
    by daith
  • Answered

    Question on duration of hsel in AHB +1

    • Timing
    • AMBA
    • AHB
    7462 views
    1 reply
    Latest over 11 years ago
    by Ben Hicks Arm Employee Badge
  • Answered

    Synchronisation Primitives and Exclusive Monitors 0

    4245 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
<>
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