I would like to know an behaviour of the interrupt on out-of-order.
In-order situation : The interrupt is issued at once because the instruction that is not completed is discarded.
Out-of-Order situation : The interrupt is not issued until the instruction that is executing is completed. For example, under the below condition,
calculation instruction
|
simple instruction
If the simple instruction can bypass many calculation instructions, the interrupt is not issued until all calculation instructions completed.
Is my understanding right? If my understanding is right, In-Order pipeline is better performance than Out-of-Order pipeline.
How do you think about this?
Best regards,
Michi
Hi,
Thank you for your comment.
I would like to confirm your comment. Is the below my understanding right?
* When an interrupt is issued, the interrupt is executed at once without the completion of the instruction.
* ARM's "result queue" is same as the retirement buffer.
* There are instructions in result queue that is completed execution and is waiting to write to register files.
* When an interrupt is issued, all instructions in result queue are discarded.
* After the interrupt execution is completed, all instructions was included in result queue is executed again without re-fetch instructions.
If my understanding is wrong, please advise me it.