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Question on duration of hsel in AHB

bax

Hi,

My question is about duration of hsel in AHB. While performing a write operation to a particular slave, if hsel for the slave is asserted (hsel=1) in the address
face and is deasserted (hsel=0) in the data phase, will it guarantee that data is written to the slave? Is it sufficient asserting 'hsel' in address phase alone ?

Please explain how the hsel should be used to ensure a correct read/write operation.

  • +1 Arm Employee Badge

    Hi Bax,

    HSEL is just a combinatorial decode of the current HADDR value - it is an address timed signal. The logic that routes HWDATA and HRDATA will function from a delayed version of HSEL, aligned with the data phase. So if you start address phase (n+1) which is targeting another slave, HSEL will show that. However, the mux/demux logic for HWDATA and HRDATA will be driven by a delayed version of HSEL which was seen for address phase N.

    Hope that helps.

    Ben