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LDM/STM interruption of Cortex-M7.

Yasuhiko Koumoto

Hi Cortex-M7 specialists.

I would like to know the Cortex-M7 behaviors when requested interrupts.
In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be prohibited by An Auxiliary Control Register).
In the Cortex-M7 case, is it the same as Cortex-M3?

Best regards,
Yasuhiko Koumoto.

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  • 0 Arm Employee Badge

    Hi,

    If an interrupt arrive at LDM/STM instruction, the instruction would be suspended and current state of the transfer would be saved to ICI bits in the PSR, so that it can resume from this one after the ISR (same as Cortex-M3).

    If an interrupt arrive at UDIV/SDIV instruction, the instruction would be abandoned restart after the ISR (same as Cortex-M3).

    However, the choice to disable interrupt in the middle of mult-cycle instruction is not available on Cortex-M7.

    regards,

    Joseph

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  • 0 Arm Employee Badge

    Hi,

    If an interrupt arrive at LDM/STM instruction, the instruction would be suspended and current state of the transfer would be saved to ICI bits in the PSR, so that it can resume from this one after the ISR (same as Cortex-M3).

    If an interrupt arrive at UDIV/SDIV instruction, the instruction would be abandoned restart after the ISR (same as Cortex-M3).

    However, the choice to disable interrupt in the middle of mult-cycle instruction is not available on Cortex-M7.

    regards,

    Joseph

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