We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating the registers SETENA / ClrEnable and SetPend / ClrPend.
For example, being the interrupt # 5 (Exception # 21) not implemented at the hardware level, this could be used as an interrupt / exception of software?
Hi Carlos,
It depends on which processor you are using:
In the Cortex-M0, Cortex-M3 and Cortex-M4 processors, a spare interrupt in the middle (e.g. IRQ 0 to 15 implemented, IRQ #5 not used) can still be used by software. The interrupt input pin is tied to 0 but the interrupt pending status and priority logic is still there.
In the Cortex-M0+ processor, we've added a configuration option for chip designers to remove unused interrupt hardware. Chip designers can choose to use this feature to reduce gate count, or leave the spare interrupt in. You can test by setting the enable bit and see if the read back value is 1.
One more thing to add about comparing using SVC with using spare IRQs for software interrupt:
SVCall exception is a synchronous exception. It means the instructions behing the SVC will not get executed and will wait for the SVC handler to complete first.
If you use IRQ as software interrupt, a couple of instructions after the setting of pending status/enabling of the interrupt could still be executed before entering the ISR. This topic is covered in Application Note
ARM Cortex-M Programming Guide to Memory Barrier Instructions
See section 4.5
ARM Cortex-M Programming Guide to Memory Barrier Instructions: 4.5. Enabling Interrupts using NVIC
Also, if the IRQ is blocked by PRIMASK or other interrupt masking registers, the program will just continue. If the SVC is blocked you would get a HardFault. As long as you handle these situations in software, yes, you can use a spare IRQ as software interrupt/exception.
regards,
Joseph
I think this is really a cool feature.
-I immediately thought of a context-switcher which is normally switched by a timer-interrupt, but can also be switched by a SVCall.
Whether or not it's a good idea to do so, I do not know. A timer could of course also be triggered by the SVCall setting a pending-bit.
...Setting the pending bit has an advantage over a few other solutions:
You won't get any race-conditions; eg. your context-switcher will not be invoked while it's about to switch, since the interrupt's priority will guard against that.
In addition, tail-chaining will be utilized.
Well, we have PendSV exception for that too! (it is available in all Cortex-M based microcontrollers, so it is more portable)
Hi Carlos-san,
is to use NVIC_ISPR register for occurring the interrupt #5 not your intention?
For example,
*(int*)0xe000e100=(1<<5); // Interrupt enable*(int*)0xe000e200=(1<<5); // Interrupt pending.
Best regards,Yasuhiko Koumoto.
If I understand the question correctly, you want to create an interrupt service routine (for instance a timer or a DMA-completion routine), which uses an unused interrupt vector in the exception vector area, thus you will be emulating an interrupt, is that understood correctly ?
I believe you may store anything you like in unused vectors, even counter-values and other variables.
(The answers below says that it's possible to trigger the interrupt by setting the pending bit on some implementations, so hereby I correct my answer to inform that there's of course no need to go the extra mile and execute the code manually if the microcontroller supports the triggering via the pending-bit).