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Out-of-Order of Cortex-A15 core and an interrupt

I would like to know an behaviour of the interrupt on out-of-order.

In-order situation :  The interrupt is issued at once because the instruction that is not completed is discarded.

Out-of-Order situation : The interrupt is not issued until the instruction that is executing is completed. For example,  under the below condition,

calculation instruction

calculation instruction

calculation instruction

                |

calculation instruction

simple instruction

If the simple instruction can bypass many calculation instructions,  the interrupt is not issued until all calculation instructions completed.

Is my understanding right? If my understanding is right, In-Order pipeline is better performance than Out-of-Order pipeline.

How do you think about this?

Best regards,

Michi

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