I would like to know an behaviour of the interrupt on out-of-order.
In-order situation : The interrupt is issued at once because the instruction that is not completed is discarded.
Out-of-Order situation : The interrupt is not issued until the instruction that is executing is completed. For example, under the below condition,
calculation instruction
|
simple instruction
If the simple instruction can bypass many calculation instructions, the interrupt is not issued until all calculation instructions completed.
Is my understanding right? If my understanding is right, In-Order pipeline is better performance than Out-of-Order pipeline.
How do you think about this?
Best regards,
Michi
It is always tricky to describe how this works and have it apply to all possible situations, simply because the Cortex-A15 and similar ARM processors are very complex devices. At a high level, in an out-of-order pipeline, consider the instruction sequence you show above: even though the simple instruction may have "completed" before the calculation instruction that appears before it in program order, the simple instruction that has "completed" is not yet "retired". What is important to realize is that instructions are "retired" in program order.
So if an interrupt occurs before the calculation instruction is complete, the exception mechanism can still preempt the calculation instruction; what would happen, though, is that up on returning from the exception, the execution would resume with the calculation instruction that was preempted... which does imply that the simple instruction would execute again. However, this does not cause an issue with the proper function of the instruction sequence.
Is there a priority assigned to the "simple instr", and also to each of the "calc instr"? If so, perhaps irq is not needed, and the OoO pipeline will have better performance after all. Just a thought.
Hi,
Thank you for your comment.
I would like to confirm your comment. Is the below my understanding right?
* When an interrupt is issued, the interrupt is executed at once without the completion of the instruction.
* ARM's "result queue" is same as the retirement buffer.
* There are instructions in result queue that is completed execution and is waiting to write to register files.
* When an interrupt is issued, all instructions in result queue are discarded.
* After the interrupt execution is completed, all instructions was included in result queue is executed again without re-fetch instructions.
If my understanding is wrong, please advise me it.
Unfortunately I don't understand your comment meaning. Please describe your comment.