Hi Cortex-M7 specialists.
I would like to know the Cortex-M7 behaviors when requested interrupts.In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be prohibited by An Auxiliary Control Register).In the Cortex-M7 case, is it the same as Cortex-M3?
Best regards,Yasuhiko Koumoto.