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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3582 Questions
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  • Not Answered

    fpga synthesis guide 0

    946 views
    0 replies
    Started over 2 years ago
    by rtung
  • Suggested Answer

    Directly Accessing Cycle Counter From Guest VM 0

    • virtualization
    1344 views
    2 replies
    Latest over 2 years ago
    by Jay M.
  • Not Answered

    L2ACTLR[7] bit need to set on power SBL on or in application is also possible 0

    1517 views
    4 replies
    Latest over 2 years ago
    by CerysDavison
  • Not Answered

    Difference between the CPU_CYLES and PMCCNTR_EL0 0

    • CoreSight Architecture
    • performance analysis
    • Arm64
    1158 views
    0 replies
    Started over 2 years ago
    by nizam.ahmed
  • Answered

    If the program size is large, it cannot be linked normally (Cortex-A55) 0

    • Cortex-A55
    • Armv8-A
    • DS-5 Ultimate Edition
    2696 views
    3 replies
    Latest over 2 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Using stage 2 translation for VMs and stage 1 translation for native applications in the same system +1

    • virtualization
    • Memory Management Unit (MMU)
    2799 views
    4 replies
    Latest over 2 years ago
    by Borna
  • Not Answered

    How to check firmware code coverage in RTL simulation phase? 0

    • Cortex-M0
    • firmware
    1533 views
    1 reply
    Latest over 2 years ago
    by Mary Herring
  • Suggested Answer

    ARMV7 PMU event counter always return 0 0

    2181 views
    6 replies
    Latest over 2 years ago
    by Lico.yu
  • Suggested Answer

    M55 System Counter & System Timer register map html/xml request 0

    1662 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Dual A53 cluster, MMU configuration 0

    2106 views
    4 replies
    Latest over 2 years ago
    by Majid Ghameshlu
  • Answered

    Generic Timer IRQ Handling 0

    • GICv3/v4
    2038 views
    3 replies
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex-M3 unintentionally translates addresses 0

    • Armv7-M
    • Cortex-M3
    2231 views
    6 replies
    Latest over 2 years ago
    by giorno2001
  • Not Answered

    ARM64 - Simple EL2 MMU Configuration 0

    • EL2
    • Memory Management Unit (MMU)
    • Arm64
    1433 views
    0 replies
    Started over 2 years ago
    by Lloyd
  • Not Answered

    Can IERRR bit recover before GIC configure ? 0

    • GICv3/v4
    • CoreLink GIC-600
    • CoreLink GIC-600 Generic Interrupt Controller
    • Generic Interrupt Controller
    • CoreLink GIC-600AE
    841 views
    0 replies
    Started over 2 years ago
    by Namu
  • Not Answered

    Point of Serialization location 0

    • Out-of-order Execution
    • AMBA 5
    1395 views
    0 replies
    Started over 2 years ago
    by Shaibal Ghosh
  • Not Answered

    Channel Dependencies for Home Node (HN) in CHI 0

    • AMBA 5 CHI
    1462 views
    0 replies
    Started over 2 years ago
    by madman
  • Not Answered

    Retry support in CHI 0

    • AMBA 5 CHI
    1579 views
    0 replies
    Started over 2 years ago
    by madman
  • Answered

    Interrupt Handling recommendation and spurious IRQ debugging 0

    • GICv3/v4
    • ARMv8 Exception Model
    2913 views
    1 reply
    Latest over 2 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Who actually does the out of ordering of the memory accesses in MPCore? 0

    • Out-of-order Execution
    1264 views
    0 replies
    Started over 2 years ago
    by Shaibal Ghosh
  • Not Answered

    Cortex-A72 ACP deadlock issue 0

    1191 views
    1 reply
    Latest over 2 years ago
    by Annie
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