• State Not Answered
  • Locked Locked
  • Replies 0 replies
  • Subscribers 349 subscribers
  • Views 672 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Can IERRR bit recover before GIC configure ?

Namu

Hi,

I am checking the GICD_IERRR bit before the GIC and GICT configuration.

Flow is as follows

1) Check the GICD_IERRR during boot sequence.

2) Intialise the GIC register.

3) configure the GICT

In step 1 , found the GICD_IERRR bit is set. Found the recovery mechanism from Spec : Arm® CoreLink  GIC-600 Generic Interrupt Controller Revision: r1p6" Page 84 for SPI SRAM. 

Can I do recovery mechanism in step 1 when IERRR bit set?  Is it showing SRAM hardware issue which can not be recover? Is recovery mechanism is applicable only when GICT catch the error?