Who actually does the out of ordering of the memory accesses in MPCore?

Hello  Ash Wilding and ARM experts,

I have gone through a presentation on memory ordering for Xen project. (https://www.youtube.com/watch?v=2I8OHacills&ab_channel=TheXenProject)

I have some basic doubt

As per my current understanding from the A57 and A78 TRM, micro ops can be issued out of order to 1 among the several execution pipelines.

This is instruction reordering for independent instruction as far as I understood.

Memory access reordering is something which means observers and slaves in a system may observe memory accesses in different sequence compare to the program sequence. This could mean 1 of the following - 

1 - CPU reordered the memory access micro ops and issued to the load and store pipelines. Interconnect(ACE/CHI) did not do any reordering

2 - CPU issues the microops in program order but Interconnect(ACE/CHI) reordered it

• Is my understanding correct?
  • If yes, then will the barrier instruction halt the CPU pipeline by stopping further instruction issue or Interconnect throttles the CPU master interface till Barrier instruction response is received?
• If not, then could you please point out to me some document which clearly corelates instruction ordering in pipeline and memory access reordering in the system?

Thanks,

Shaibal