Please note: We are aware of an issue affecting replies on the Arm Community forums, which may not be loading as expected.
We apologize for any inconvenience and appreciate your patience while we investigate and work to resolve the issue.
Thank you for your understanding.
Can you share any examples of write access Cortex-A72 ACP port deadlocks? What are the limitations of using ACP ports at the system level, except for those mentioned in the A72 TRM manual
Hi there, I have moved your question to the Architectures and Processors forum. Many thanks.