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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Inquire about the official DMIPS/MHz value for Cortex A53. 0

    • Cortex-A53
    2830 views
    0 replies
    Started over 1 year ago
    by daehyunyoon
  • Suggested Answer

    How many cycles will CYCCNT count during CPU halt? 0

    1565 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cacheable=0 vs Shareable=1 0

    • Cache coherency
    • Cortex-R5
    • Memory Protection Unit (MPU)
    2018 views
    2 replies
    Latest over 1 year ago
    by AakashKedia22
  • Suggested Answer

    Cortex R52+ typical interrupt latencies 0

    1264 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex X4/A720/A520 optimization guides? 0

    2727 views
    1 reply
    Latest over 1 year ago
    by George Steed Arm Employee Badge
  • Not Answered

    About Arm Contex-A53 pipeline architecture 0

    • AArch64
    • Learn the Architecture
    • Processor Architecture
    1114 views
    0 replies
    Started over 1 year ago
    by Robinz
  • Answered

    ARM STL Availability 0

    1879 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Managing an 8-bit variable instead of a 32-bit variable (Cortex-M4) 0

    • Cortex-M
    • Cortex-M4
    2512 views
    2 replies
    Latest over 1 year ago
    by FlavioB
  • Suggested Answer

    Startup file for CortexR52 0

    1151 views
    1 reply
    Latest over 1 year ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    Return stack behavior when it's disabled 0

    702 views
    0 replies
    Started over 1 year ago
    by Youq
  • Not Answered

    Cortex A9 MMU Cache initialization 0

    • Cortex-A9
    • System MMU
    902 views
    0 replies
    Started over 1 year ago
    by prahsman
  • Answered

    GIC dynamic interrupt priority change -- possible? 0

    • GICv2
    • GICv3/v4
    • Emulation & Virtualization
    3516 views
    4 replies
    Latest over 1 year ago
    by Cyril Novikov
  • Suggested Answer

    A9 MMU Questions 0

    • Cortex-A9
    1017 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Armv8-A - Using watchpoints (DBGWVR<n>_EL1) with Intermediate Physical Addresses (IPA) 0

    • AArch64
    • virtualization
    • Armv8-A
    • Debugging
    • Hypervisor
    • Memory Management
    1450 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How to evaluate DSU performance 0

    2409 views
    2 replies
    Latest over 1 year ago
    by Veerender
  • Not Answered

    outperformance of ETM with recent cortex M cores? 0

    • ETM
    • Cortex-M7
    • Trace macrocells
    • CoreSight ETM-M7
    • Debug and Trace
    858 views
    0 replies
    Started over 1 year ago
    by mastupristi1
  • Not Answered

    Data trace in Cortex M85 0

    • ETM
    • Cortex-M85
    624 views
    0 replies
    Started over 1 year ago
    by mastupristi1
  • Not Answered

    performance monitor unit real time related 0

    • Cortex-A9
    • Cortex-A
    749 views
    0 replies
    Started over 1 year ago
    by WatterCutter
  • Answered

    Clean dcache when dcache disabled 0

    1507 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex A9 MP MMU 0

    2384 views
    2 replies
    Latest over 1 year ago
    by Annie
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