Hi everybody,
I am trying to read back data in the A53 L1 data cache through the technique in TRM "6.7 Direct access to internal memory".
I noticed even when I read a block of memories sequentially, the values I read back showed the way 0-3 allocation is unpredictable.
Is it randomly allocated? I heard of something being random somewhere.
Thank you.
User_0182
Maybe it's the replacement policy is pseudo-random and result in way allocation being random.
Hi User_0182,
This is correct. Quoting the Cortex-A53 TRM Data side memory system chapter:
The data cache has the following features:
Pseudo-random cache replacement policy.
Thank you vstehle.