Hi Community,
I am trying to disable the hardware prefetchers on arm cortex A57. This includes and cache line preftching or any other data pefetching etc.
I am aware of ARM's exception levels and the fact that i might have to tweak bootloader itself.
Some set of blogs, specific registers to set/unset etc. or some flowchart regarding this specific/ similar problem would be a great assistance.
if anyone could help regarding this , then it would solve a long standing problem for me.
Regards
Shikhar Jain.
ShikharJain said:I am trying to disable the hardware prefetchers on arm cortex A57.
Why?
The architecture gives you some controls for limiting speculation, for example the execute-never attributes to control where instructions are prefetched from. Similarly, marking regions as Device prevent data access speculation.
There are also some processor specific controls described in the TRM:
https://developer.arm.com/documentation/ddi0488/h/system-control/aarch64-register-summary/aarch64-implementation-defined-registers?lang=en
But whether of these approaches are likely to help depends on what problem you're trying to solve.
Martin Weidmann Thanks for the reply. I am just curious to expand further on the advice related to "marking regions as Device prevent data access speculation".
Is this possible to read/write any such set of registers via code itself(i.e controlling data prefetching from user-space without tweaking bootloader etc.). Or it would be great if you have any such examples.
Shikhar.
ShikharJain said:i.e controlling data prefetching from user-space without tweaking bootloader etc
The controls that impact prefetching/speculation require EL1 or greater privilege (so OS or above). The MMU translation tables control the Type (Normal vs Device) and Permissions (R/W/X). Marking a region as Device blocks data speculation. Marking a region as not executable blocks instruction prefetching.
A given processor might have IMPDEF controls to tune/tweak prefetching, you'd need to check the individual Technical Reference Manuals. But all such controls I'm aware of require EL1 or greater privilege.
What you can use in EL0 (user space) is the cache prefetch instructions. But these are usually to tell the processor that it should prefetch something, which I think is the reverse of what you want. Plus, the cache prefetch instructions need to be used carefully and sparingly. Often the automatic prefetchers will do a better job on their own, the prefetch instructions can be useful for the first iteration to help them learn.
Which brings me back to my original question, why are you looking to disable speculation?
hi martin. i am trying to benchmark caches to measure quantities like communication bandwidths, misses etc. Thus it is crucial (as suggested by academic research) to disable any data prefetching(at least) . For intel desktop/workstation cpus, this is easy to control. But i cannot wrap my head around how this would be achieved in the case of ARM CPUs.
I am curious, wether any common workflow exists for this particular problem in the case of arms cpu's . If possible, please share high-level steps(or any other resources) to disable them from the bootloader level. i want them to be disabled system-wide.