Greetings,
my application scenarios
SOC: Dual core cortex-a7 with shared 512K L2 cache
os/app: AMP, one core for rtos another for linux, and the two app have no relationship concurrently
Ok, for improving realtime response time on rtos side, usually make shared cache lockdown config in my old products, for eg. L2cc-pl310 in dual-a9 zynq7000 platform, for armv8-a55 based with an L3 dsu etc.
But I found that, the a7 core does not use external l2cc, seemingly the L2 cache logic is cores binded. And there is no detailed info in CP15 control in TRM, it said it is implementation spec.
This dual-a7 soc manufacture does not provide info about this, or, should it?
Clearly, How do the shared L2 cache partitioning in dual-a7 soc? thanks.
duanlin@china.tianjin 2024-5-28
Can you ask the SoC vendor whether or not the dual-core Cortex-A7 SoC integrates the PL310 Cache Controller IP? This information should come from the SoC vendor.