Hello,
I am using Pseudo-fault Generation Control Register(ERR0PFGCTL) of FEAT_RASv1p1 to inject SError exception for testing purposes on FVP platform.
I am able to inject an Uncorrected Error Type(UE) from EL1 and take the exception at EL2. But somehow for Corrected(CE) and Deferred(DE) errors, the SError exception does not trigger even though it seems to be correctly recorded in ERR0STATUS.CE/DE. any ideas why the exception is not taken for CE/DE errors?
What I really want is to inject a containable error that will be deferred at EL2 entry because of an ESB instruction so that I can read the differed error from DISR_EL1. Currently, whenever I inject a DE error + ESB, the DISR_EL1 reads zero.
Thanks in advance.
As it says, this is "implementation specific" behavior. Whether this is supported depends heavily on the implementation. The CPU is very unlikely to support injection of an error state that it wouldn't reach on a real fault.