How does the Cortex M0+ pipeline handle a branch instruction to an address that is not 32-bit aligned?

It is my understanding that the M0+ pipeline can fetch 2 16-bit instructions in a single cycle. Does that still apply if we branch to an address that isn't 32-bit aligned? 

For example, if we branch to address 0x00302, will the M0+ on that next cycle fetch the instructions at both 0x00302 and 0x00304? Or will it only fetch 0x00302 on that cycle and then get 0x00304 and 0x00306 the next time?