Regarding the order of interrupt requests

The CPU used is S32K148(Cortex-M4).

While processing interrupt A, a PendSV exception is intentionally generated while interrupts are disabled (faultmask).
The priority is PendSV > interrupt A.
Since interrupts are disabled, the process does not immediately switch to PendSV; instead, processing interrupt A continues, and when processing interrupt A finishes, interrupts are enabled and the process transitions to PendSV.

Normally, this processing works as expected, but it seems that if another interrupt B occurs in the interrupt disabled section where PendSV is generated, it behaves unexpectedly.
The priority is PendSV > interrupt B > interrupt A.
Because PendSV and interrupt B occur in the interrupt disabled section, interrupt A processing will continue for a while.
When interrupt A processing finishes and interrupts are enabled, it appears that interrupt B is accepted before PendSV.

In the above case, it is assumed that PendSV will be accepted before interrupt B.
To ensure that PendSV is accepted first, the DMB instruction is executed after writing 1 to the PENDSVSET bit in the ICSR register.

Are there any possible reasons for this?

Incidentally, interrupt A and interrupt B are periodic interrupts of FTM on different channels.