Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3632 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
    1253 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
    2345 views
    6 replies
    Latest over 1 year ago
    by ele
  • Not Answered

    Is there any way to use 2-DSU IPs in a same NI-Bus ? 0

    • DSU-120
    • DSU
    424 views
    0 replies
    Started over 1 year ago
    by Sangu Park
  • Answered

    Secure Mode Switching in R5 0

    • cortexr5
    1025 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
    • Cortex-A
    426 views
    0 replies
    Started over 1 year ago
    by yiduan su
  • Answered

    What will happen when cacheline is mismatch 0

    • Cache
    • Cache Management
    • Cortex-A
    • Cortex-M
    1333 views
    2 replies
    Latest over 1 year ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    1071 views
    1 reply
    Latest over 1 year ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    611 views
    0 replies
    Started over 1 year ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
    • Armv8-A
    • Cortex-A
    2140 views
    5 replies
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1921 views
    5 replies
    Latest over 1 year ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    1152 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    914 views
    1 reply
    Latest over 1 year ago
    by steve jeong
  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1578 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    461 views
    0 replies
    Started over 1 year ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    2150 views
    0 replies
    Started over 1 year ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    2479 views
    3 replies
    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    522 views
    0 replies
    Started over 1 year ago
    by Abdelrahman Ehsan
  • Suggested Answer

    Enable exceptions for dividing by zero float for CORTEX R7 0

    • Exception Handling
    • division by zero
    • Cortex-R
    • Floating-Point Execution
    • Cortex-R7
    1146 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Are Stage 1 & 2 walk repeat loops bounded? 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    3162 views
    5 replies
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Does integrated MCU consume memory bandwidth extremely, within a (Quad-A55 + MCU) SOC ? 0

    524 views
    0 replies
    Started over 1 year ago
    by duanlin
<>