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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    1958 views
    0 replies
    Started 11 months ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    2349 views
    3 replies
    Latest 11 months ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    507 views
    0 replies
    Started 11 months ago
    by Abdelrahman Ehsan
  • Suggested Answer

    Enable exceptions for dividing by zero float for CORTEX R7 0

    • Exception Handling
    • division by zero
    • Cortex-R
    • Floating-Point Execution
    • Cortex-R7
    1088 views
    1 reply
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Are Stage 1 & 2 walk repeat loops bounded? 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    3098 views
    5 replies
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Does integrated MCU consume memory bandwidth extremely, within a (Quad-A55 + MCU) SOC ? 0

    508 views
    0 replies
    Started 11 months ago
    by duanlin
  • Answered

    Amount of data that can be sent with one CMSIS-DAP data transfer command 0

    • DAP
    • CMSIS
    • CoreSight
    2409 views
    6 replies
    Latest 11 months ago
    by Oom Sats
  • Suggested Answer

    ARMv8 Cortex-A55 How to enable cache protection behavior 0

    • AArch64
    • Cortex-A55
    • Cache
    • Armv8-A
    1151 views
    1 reply
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    ARM CCA 0

    • cca
    1162 views
    1 reply
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    How is cache addressing assigned on the R5? 0

    • Cortex-R5
    1595 views
    3 replies
    Latest 11 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    A53 NEON memory access behavior 0

    • AXI4
    • Armv8-A
    • NEON
    • a53
    788 views
    1 reply
    Latest 11 months ago
    by Dylan Barrie
  • Answered

    Cortex-M33 wake up from SLEEPDEEP 0

    • nvic
    • Cortex-M33
    • Interrupt
    • WIC
    1798 views
    2 replies
    Latest 11 months ago
    by Yael Kanter-Weisman
  • Suggested Answer

    Ask a question about SME. 0

    1201 views
    1 reply
    Latest 11 months ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    CHI TXLINK state deadlock possibility 0

    2047 views
    3 replies
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Cleaning BSS in ARMv8-A 0

    • Clean
    • BSS
    • Cortex-A
    859 views
    1 reply
    Latest 11 months ago
    by Mahmud Esad Çıtak
  • Suggested Answer

    Is it possible to use the DBID as a conforming acknowledgement in CHI OWO process? 0

    • CHI
    • order
    1808 views
    2 replies
    Latest 11 months ago
    by Ming Gao
  • Suggested Answer

    AREADY/ARVALID and AWREADY/AWVALID for subsequent transfers in a burst 0

    1272 views
    1 reply
    Latest 11 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    GIC-600 ITS MSI Handling: Who Writes the INT Command in the Command Queue? 0

    1939 views
    4 replies
    Latest over 1 year ago
    by steve jeong
  • Not Answered

    Arm CortexR-52 SBIST user guide 0

    523 views
    0 replies
    Started over 1 year ago
    by Akshansh Aswal
  • Suggested Answer

    Ordering of Memory-mapped device control with payloads 0

    • Architecture
    • Armv8
    • Memory
    3650 views
    7 replies
    Latest over 1 year ago
    by Alwin Joshy
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