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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Not Answered

    Barriers in in-order cores like cortex-A53, A7 0

    • Cortex-A53
    • Cortex-A
    • Cortex-A7
    8476 views
    4 replies
    Latest over 9 years ago
    by oootha
  • Answered

    RTC and Watch dog timer CMSIS driver API 0

    • CMSIS
    6333 views
    1 reply
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    which ARM version that i should use for PLC +1

    • Cortex-R
    • Cortex-A
    • Cortex-M
    12745 views
    6 replies
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    Memory partitioning on Cortex-A7 0

    • Security
    • CortexA7
    • Cortex-A
    • TrustZone
    • Baremetal
    • Memory
    • Linux
    5566 views
    3 replies
    Latest over 9 years ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    cortex A9 multi-core 0

    • Cortex-A9
    • Cortex-A
    4337 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Cortex M3 peripheral Bit Banding limit? 0

    • Cortex-M3
    • Cortex-M
    21256 views
    18 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    ETM not working on stm32f7 +1

    • Cortex-M
    4438 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    real time digital signal processing and its performance analysis 0

    • Cortex-M3
    • Cortex-M
    • CMSIS
    4353 views
    2 replies
    Latest over 9 years ago
    by Amit
  • Not Answered

    Using the whole Cortex-A L2 Cache without external memory 0

    • Cache
    • Cortex-A
    • Cortex-A7
    24831 views
    16 replies
    Latest over 9 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    cortex m0 0

    • Cortex-M0
    • Armv6-M
    • Cortex-M
    4654 views
    2 replies
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    What is the meaning of a 64 bit aligned stack pointer address? 0

    • Armv6-M
    • Armv7-M
    • Cortex-M
    • Cortex-M4
    22527 views
    10 replies
    Latest over 9 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    why some instructions are not required to be  explicitly synchronized ? +1

    • Armv8
    4590 views
    2 replies
    Latest over 9 years ago
    by shengyu shen
  • Answered

    PSP Stack Pointer, what memory address does it point to? 0

    • Cortex-M
    • Cortex-M4
    16958 views
    5 replies
    Latest over 9 years ago
    by Murtuza Quaizar
  • Answered

    How to get the secure(or non-secure) state on Cortex-A53? 0

    • Cortex-A53
    • Armv8
    • Cortex-A
    7934 views
    3 replies
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    AMBA AHB5 : Stable Between Clock Question +1

    • AMBA
    • AMBA 5
    • AHB
    6431 views
    3 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Memory controller for AHB, dual (or multi) channel +1

    • AXI
    • AHB
    5512 views
    3 replies
    Latest over 9 years ago
    by David
  • Answered

    Can I use EXEC_RETURN on M0 outside of an exeception for contect switches? +1

    • Cortex-M0
    • Armv6-M
    • Cortex-M
    2997 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    How to measure CPU utilization of ARM processors ? 0

    • Cortex-A15
    • Cortex-A
    10395 views
    1 reply
    Latest over 9 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Why does the ARM A15 processor have so many DVFS levels ? 0

    • Cortex-A15
    • Cortex-A
    6461 views
    3 replies
    Latest over 9 years ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    TM4C129 - Protect the code from copy 0

    • Cortex-M
    4995 views
    3 replies
    Latest over 9 years ago
    by Amir
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