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about tail chaning of Cortex-M0

下田敏郎

Hello.

I'm studying about the tail chaining of Cortex-M0.

Is it same as Cortex-M3 or M4?

Best regards.

Parents
  • 0 in reply to 下田敏郎

    Hello shimochan,


    do you want to know what is the tail chaining?
    If it is correct, the tail chaining means that preveios context POP and a new context PUSH will be omitted if the CPU detect another interrupt before POPing the contexts.
    As you know one interrupt sequence takes as the following procedure.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <6> Return to the interrupted position


    If the next interrupt detects at the <5> or later, the sequence wil be the following.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <*> New Interrupt
    <6> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <7> Jump to ISR
    <8> Process ISR
    <9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <10> Return to the interrupted position

    Here, the contents of <5> and <6>, and the target stack would be the same.
    Therefore. CPU wants to omit the <5> and <6> processes to avoid the extra stack handling. If the next interrupt would come just before <5>, it would be possible.
    This is the tail chaining. After all, the interrupt sequence would become the following.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <7> Jump to ISR
    <8> Process ISR
    <9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <10> Return to the interrupted position

    As the results, 4 data push and 4 data pop (i.e. 8 cycles at the minimum) could be saved.
    Can this help you?


    Best regards,
    Yasuhiko Koumoto.

Reply
  • 0 in reply to 下田敏郎

    Hello shimochan,


    do you want to know what is the tail chaining?
    If it is correct, the tail chaining means that preveios context POP and a new context PUSH will be omitted if the CPU detect another interrupt before POPing the contexts.
    As you know one interrupt sequence takes as the following procedure.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <6> Return to the interrupted position


    If the next interrupt detects at the <5> or later, the sequence wil be the following.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <*> New Interrupt
    <6> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <7> Jump to ISR
    <8> Process ISR
    <9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <10> Return to the interrupted position

    Here, the contents of <5> and <6>, and the target stack would be the same.
    Therefore. CPU wants to omit the <5> and <6> processes to avoid the extra stack handling. If the next interrupt would come just before <5>, it would be possible.
    This is the tail chaining. After all, the interrupt sequence would become the following.

    <1> Detect Interrupt
    <2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
    <3> Jump to ISR
    <4> Process ISR
    <7> Jump to ISR
    <8> Process ISR
    <9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
    <10> Return to the interrupted position

    As the results, 4 data push and 4 data pop (i.e. 8 cycles at the minimum) could be saved.
    Can this help you?


    Best regards,
    Yasuhiko Koumoto.

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