Dear sirs,
From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which is very difficult to understand.
DMB only cares about memory access ordering while DSB requires all memory access before it are finished. So what is the boundary of DMB in memory access? When can I know that DMB can finish?
In single core processor, DMB can finish when all memory access are sent to L1 memory system, is it right?
In multiple core processor, DMB can finish when all memory access are sent to L2 memory system, is it right?
While DSB is very easy to understand, DSB needs all load and store operation are finished. So all bus operations are finished and all buffer are empty, is it right?
It seems the difference of DMB and DSB in multi-core is very little.
Please correct me when there is any mistake.
Thanks.
Cray
Message was edited by: cray
Hi Daith
Thanks for your clarification. It helps me much.
cray