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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Not Answered

    My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag? 0

    • Cortex-M
    • Cortex-M4
    9689 views
    8 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    What is differene between cortex A, Cortex M and Cortex R series of ARM? 0

    • Cortex-R
    • Cortex-A
    • Cortex-M
    37778 views
    3 replies
    Latest over 9 years ago
    by tanveermalik
  • Answered

    How to configure Cortex-A57 PMU 0

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    • 64-bit
    8999 views
    5 replies
    Latest over 9 years ago
    by Michael
  • Answered

    Cannot access EL1 resources from EL3 or secure world on armv8. +1

    • Cortex-A53
    • Arm Trusted Firmware
    • Cortex-A
    • TrustZone
    9400 views
    4 replies
    Latest over 9 years ago
    by Tgn Yang
  • Answered

    AMBA AHB 0

    • AMBA
    • AHB
    8692 views
    6 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AXI3 data interleaving 0

    • AXI3
    7214 views
    2 replies
    Latest over 9 years ago
    by Utkarsh Jain
  • Not Answered

    Is it possible to implement EL3 AArch64 and change it later to EL3 AArch32? 0

    • AArch64
    • Armv8-A
    • AArch32
    5401 views
    2 replies
    Latest over 9 years ago
    by 유영현
  • Answered

    CortexA8 L2 data loss 0

    • Cache
    • Cortex-A
    • Cortex-A8
    24414 views
    23 replies
    Latest over 9 years ago
    by Andreas Hauser
  • Answered

    I'm not seeing any flush-to-zero (FTZ) effects with NEON intrinsics on an ARM A9, any advice? +1

    • Armv8-A
    • NEON
    7149 views
    3 replies
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    TZC380: AXI ID and AID_WIDTH 0

    • TZC-380
    • TrustZone Controllers
    • AXI
    • Linux
    7106 views
    3 replies
    Latest over 9 years ago
    by Vincent Siles
  • Answered

    TZASC (TZC380) enabling sequence 0

    • Cortex-A9
    • Cortex-A
    7389 views
    4 replies
    Latest over 9 years ago
    by Vincent Siles
  • Not Answered

    purpose of RSDIS in ACTLR ? 0

    • Cortex-R
    • Cortex-R4
    7390 views
    8 replies
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    In AHB, can i program HSPLITx signal from slave sequence +1

    • AHB
    3457 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    CORTEX-A processor interrupt handling +1

    • Armv7
    • Armv8
    • Cortex-A
    • AArch32
    7247 views
    1 reply
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    When are A32 state and A64 state determined? 0

    • EL1
    • Armv7
    • EL2
    • AArch64
    • EL0
    • AArch32
    7916 views
    5 replies
    Latest over 9 years ago
    by lookTEE
  • Answered

    Cache type and cache operation sequence +1

    • AMBA
    • ACE
    • Cache
    7217 views
    3 replies
    Latest over 9 years ago
    by Michael Williams Arm Employee Badge
  • Not Answered

    Cortex M7 : Exception return query 0

    • Cortex-M7
    • Cortex-M
    8193 views
    5 replies
    Latest over 9 years ago
    by Ritesh Joshi
  • Answered

    How to configure L2 cache in Cortex-A7 +1

    • Cache
    • Cortex-A
    • Cortex-A7
    8346 views
    1 reply
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    ARM Cortex M4F - Directly wiring USB Connection (Custom PCB) +1

    5549 views
    1 reply
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unk +1

    • Processor
    4834 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone