I'm not a native English speaker. So, sorry for the broken English. I'm intend to develop a system where the microcontroller will interface with a 8 bit parallel port IC. The bytes will be loaded into the microcontroller at the specific timing. As documented for the Cortex-M4 in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/CHDDIGAC.html , the example: LDR R0,[R1,R2]; STR R0,[R3,#20] - normally three cycles total.
LDR R0,[R1,R2]; STR R0,[R3,#20]
How about the timing for the Cortex-M7 same as the example ?
Hi azrul,
I'm sorry but I cannot fully answer your questions.I just show the observed results on my evaluation board.Because I am not the implementer of Cortex-M, I cannot know more than written in the documents.
So basically, M4 and M7 will execute the successive LDR & STR 's in 1 cycle ?
No. It would be applicable only to M3/M4. Also, this assumes 0 wait memory and AHB Lite bus. Cortex-M7 equips AXI bus.If you think to access GPIOs, they might not be accessed within 1 cycle.
Best regards,Yasuhiko Koumoto.